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FWD:Taiwan’s TSMC reveal details about 3nm process technology

Taiwan Semiconductor Manufacturing Company (TSMC) plans to continue expanding its use of extreme ultraviolet (EUV) lithography tools for its next-generation 3nm (N3) node process.
TSMC was the first company to use ASML’s EUV lithography machines for high-volume production and now has at least three processes that use EUV for select layers, according to Tom’s Hardware. The Taiwanese company employs EUV lithography for its N7+, N6, and N5 nodes.

TSMC’s 2nd generation 7 nm technology (N7+) uses EUV for up to four layers in order to reduce its use of multi-patterning techniques when building highly complex circuits, while the 6 nm process (N6) is for clients who looking to re-use IP designed for 1st generation 7 nm, per the report. TSMC’s 5 nm process (N5) can use EUV for up to 14 layers and is for clients who need a significant increase in transistor density in addition to performance enhancements.

Moving forward, the Taiwanese chipmaker says it plans to offer customers 2nd generation 5 nm (N5P) and 4 nm (N4) fabrication processes, which are primarily based on 5 nm technology and will have performance and power benefits. N5P is slated to become available in 2021, while N4 chips are scheduled for volume production in 2022.

When it comes to their next-generation 3 nm process (N3), it will be a full node improvement over N5. TSMC says there will be a logic density gain of up to 70 percent, an up to 15-percent performance gain, and an up to 30-percent power reduction compared to its 5-nm process. According to ASML, N3 will use EUV over 20 layers.

TSMC will use the FinFET transistor structure for their 3-nanometer chips designed for both mobile and high-performance computing applications. Risk production for their N3 node is scheduled for 2021, with volume production slated for the second half of 2022.

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